The present invention relates to communications, and in particular to a digital radio receiver lock detector for use in carrier signal recovery.
Radio architecture has remained remarkably constantxe2x80x94for fifty years radios have been designed around the classic superheterodyne approach. For example, in conventional cellular basestations, each channel has a dedicated receiver tuned exclusively to that specific channel. Each of these receivers requires a fair degree of power, size and expense. This architecture leads to a lot of expensive dedicated receivers in a basestation. Not only are these channels expensive, they are fixed/custom built for a given air interface/modulation standard (e.g., exclusively for AMPS), and tuned for a given channel setting.
However, developments in digital signal processing (DSP) and data conversion are providing radio receiver designers with the tools for more efficient architectures. For example, in the field of wireless base stations, wideband receivers have offered significant benefits, including reductions in base station cost, size, complexity, and power consumption of a basestation. In addition, wideband digital receivers can be rapidly configured to support a variety of air interface/modulation schemes and protocols (e.g., AMPS, NAMPS, TDMA, CDPD, etc.) simultaneously, and switching between them whenever required. Significantly, since the wideband digital receiver processing is performed in software (i.e., in a DSP), the receiver can easily be programmed can support new protocols as they were developed.
In a wideband receiver, the wideband signal is captured, bandshifted to IF and digitized using the single wide-band data converter, which provides a digitized IF signal. The digitized IF signal is then input to a plurality of digital tuners, which each mix and filter the digitized IF signal to recover one of the individual channels associated with the tuner. For example, if there are 60 channels each 30 kHz wide, then the receiver must have a bandwidth of at least 3.6 MHz. Advantageously, the wideband receiver is shared between all the channels, instead of having a narrow band receiver assigned to each channel. Of course, each channel still requires its own circuitry for the final processing, which is all digital.
In addition, the flexibility of the digital stage means that the basestation can be xe2x80x9creprogrammedxe2x80x9d to work with new standards. For example, some channels may operate with the conventional analog cellular standard (AMPS), while others use the newer digital IS-54 (TDMA) standard. Notably, because the decoding is performed by software, it can be changed xe2x80x9con the flyxe2x80x9d, so the mix of channels between standards can be changed as required. Indeed, even the channel becomes flexiblexe2x80x94with complete freedom to change from 30 kHz of AMPS or TDMA, to 10 kHz for NAMPS or 1.25 MHz for CDMA. This can be done channel-by-channel as desired.
Since wideband receivers are preferably programmable, each channel digital tuner must accurately lock onto the frequency it is assigned to recover.
Therefore, there is a need for a robust and accurate digital radio receiver carrier lock detector.
Briefly, according to the present invention, a digital radio tuner lock detector receives an in-phase (I) data signal and a quadrature (Q) data signal. The lock detector processes these signals to compute a data signal power estimate and integrates the data signal power estimate to provide a threshold signal value. The lock detector also includes a carrier frequency lock detector and a carrier phase lock detector. The carrier frequency lock detector receives the I and Q data signals and computes a frequency error signal and integrates the frequency error signal to provide an integrated frequency error signal. The carrier frequency lock detector compares the magnitude of the integrated frequency error signal to the threshold signal value to determine if frequency lock has been achieved and provides a frequency lock status signal indicative thereof. The carrier phase lock detector receives the I and Q data signals and computes a phase error signal and integrates the phase error signal to provide an integrated phase error signal. The phase lock detector also compares the magnitude of the integrated phase error signal to the threshold signal value to determine if carrier phase lock has been achieved.
Carrier frequency recovery occurs first and when the carrier frequency lock detector identifies carrier frequency lock, carrier phase recovery is then performed. Once the carrier phase lock detector identifies phase lock, accurately received data is available for signal processing.
The carrier frequency and phase lock detector can be applied to many multi-phase and/or multi-amplitude modulation techniques (e.g., M-PSK, M-QAM, PAM). In addition, the detector can be used in acquisition mode (i.e., transitional phase) and/or tracking mode (i.e., steady state phase). The detector can especially enhance the performance of non-decision-aided feedback loop systems.
The detector may be employed in either full digital demodulators (i.e., parameter estimation and correction are performed digitally) or hybrid demodulators (i.e., parameter estimation is performed digitally and carrier frequency and phase correction are performed in the continuous time domain).
These and other objects, features and advantages of the present invention will become apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.